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1/22 january 2001 n fully integrated afe for cpe adsl n overall 12 bit resolution, 1.1mhz signal bandwidth in rx n 8.8ms/s adc n 8.8ms/s dac n thd: -60db @full scale n 4-bit digital interface to/from the dmt modem n 1v full scale input n differential analog i/o n accurate continuous-time channel filtering n 3rd & 4th order tunable continuous time lp filters n 0.5 watt at 3.3v n 0.5mm hcmos5 la technology n 64 pin tqfp package description st70134 is the analog front end of the stmicro- electronics ascot tm adsl chipset and when coupled with st70135a or st70235 (dmt modem) allows to get a t1.413 issue 2 or g.dmt compliant solution. the st70134 analog front end handles 2 trans- mission channels on a balanced 2 wire intercon- nection; a 16 to 640kbit/s upstream transmit channel and a 1.536mbit/s to 8.192mbit/s down- stream receive channel. this asymmetrical data transmission system uses high resolution, high speed analog to digital and digital to analog conversion and high order analog filtering to reduce the echo and noise in both receivers and transmitters. external low noise driver and input stage used with st70134 guarantee low noise performances. the filters, with a programmable cutoff frequency, use automatic continuous time tuning to avoid time varying phase characteristic which can be of dramatic consequence for dmt modem. it requires few external components, uses a 3.3v supply. it is packaged in a 64-pin tqfp in order to reduce pcb area. tqfp64 ordering number: st70134 (tqfp64) ST70134A (tqfp64) st70134 - ST70134A ascot tm integrated adsl cmos analog front-end circuit
ST70134A 2/22 figure 1 : block diagram the receiver (rx) part the dmt signal coming from the line to the st70134 is first filtered by two external filters, pots hp and channel filters. an analog multiplexer allows the selection between two input ports which can be used to select an attenuated (0, 10db for ex.) version of the signal in case of short loop or large echo. the signal is amplified by a low noise gain stage (0-31db) then low-pass filtered to avoid aliasing and to ease further digital processing by removing unwanted high frequency out-of-band noise.a 13-bit a/d converter samples the data at 8.832ms/s (or 4.416ms/s in alternative mode), transforms the signal into a digital representation and sends it to the dmt signal processor via the digital interface. the transmitter (tx) part the 12-bit data words at 8.832ms/s (or 4.416ms/ s) coming from the dmt signal processor through the digital interface are transformed by d/a con- verter into a analog signal. this signal is then filtered to decrease dmt side- lobes level and meet the ansi transmitter spectral response but also to reduce the out-of-band noise (which can be echoed to the rx path) to an acceptable level. the pre-driver buffers the signal for the external line driver and in case of short loop provide attenuation (-15...0db). the vcxo part the vcxo is divided in a xtal driver and a auxil- iary 8 bits dac for timing recovery.the xtal driver is able to operate at 35.328mhz. the dac which is driven by the ctrlin pin pro- vides a current output with 8-bit resolution and can be used to tune the xtal frequency with the help of external components. a time constant between dac input and vcxo output can be introduced (via the ctlin interface) and programmed with the help of an external capacitor (on vcoc pin).see chapter 'vcxo' for the external circuit related to the vcxo. the digital interface part the digital part of the st70134 can be divided in 2 sections: C the data interface converts the multiplexed data from/to the dmt signal processor into valid representation for the tx dac and rx adc. C the control interface allows the board processor to configure the stl70134 paths (rx/tx gains, filter band, ...) or settings (osr, vcodac enable, digital / analog loopback,...). r-mos-c tuning i/v-ref xtal-driver vcxo dac g = -15...0db step = 1db agctx txp txn 1.1mhz hc2 1.1mhz hc1 138khz sc2 digital if dac agcrx g = 0...31db step = 1db rxp(0:1) rxn(0:1) adc 13 bits 12 bits rx (0:3) tx (0:3)
ST70134A 3/22 dmt signal (done by the dmt companion chip) a dmt signal is basically the sum of n indepen- dently qam modulated signals, each carried over a distinct carrier. the frequency separation of each carrier is 4.3125khz with a total number of 256 carriers (ansi). for n large, the signal can be modelled by a gaussian process with a certain amplitude probability density function. since the maximum amplitude is expected to arise very rarely, we decide to clip the signal and to trade-off the resulting snr loss against ad/da dynamic. a clipping factor (vpeak/vrms = "crest factor") of 5.3 will be used resulting in a maximum snr of 75db. adsl dmt signals are nominally sent at an aver- age of -38dbmhz (-1.65dbm/carrier) with a maxi- mal power of 15.7mw for the transmitter (upstream for adsl over pots, dmt carriers are from 7 to 31, for adsl over isdn dmt carriers are from 31 to 64). maximum / minimum signal levels the following table gives the transmitted and received signal levels for cpe (atu-r) and, for reference, at atu-c. all the levels are referred to the line voltages (i.e. after hybrid and transform- ers in tx direction, before hybrid and transformer in rx direction). note that signal amplitudes shown below are for illustration purpose and depending on the transmit power and line impedance signal amplitudes can differ from these values. the reference line impedance for all power calcu- lations is 100 w . package the st70134 is packaged in a 64-pin tqfp pack- age (body size 10x10mm, pitch 0.5mm). * power cut back software co facility. table 1 : target signal levels (on the line) parameter atu - r atu - c (for reference) rx tx rx tx max level 3.95 vpdif * 6.8 vpdif 1.66 mvpdif 15.8 vpdif * max rms level 791 mvrms 671 mvrms 168 mvrms 3.16 vrms min level 42 mvpdif 839 mvpdif 54 mvpdif 3.95 vpdif min rms level 8 mvrms 168 mvrms 11 mvrms 791 mvrms
ST70134A 4/22 figure 2 : pin connection 58 57 56 55 54 53 52 51 50 49 64 63 62 61 60 59 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 23 24 25 26 27 28 29 30 31 32 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tx2 tx3 dvss2 avss1 xtalo xtali avdd1 res vcxo ivco avdd2 iref avss2 avss6 rxip1 rxin1 dvdd2 pdown res resetn res gp0 avss3 vrap vref vran avdd3 avdd4 nc0 nc1 txp txn rxip0 rxin0 gc1 gc0 vcoc gp2 avdd6 avdd5 res res agnd res res avss5 avss4 gp1 tx1 tx0 nu3 nu2 nu1 nu0 ctrlin dvss1 clkm clnib clwd rx3 rx2 rx1 rx0 dvdd1 st70134
ST70134A 5/22 table 2 : pin functions numbers name function pcb connection supply analog interface 24 vrap positive voltage reference adc decoupling network avdd3 25 vref ground reference adc decoupling network avdd3 26 vran negative voltage reference adc decoupling network avdd3 31 txp pre driver output line driver input avdd4 32 txn pre driver output line driver input avdd4 38 agnd virtual analog ground (avdd/2 = 1.65v) decoupling network avdd5 44 vcoc vcodac time constant capacitor vcodac cap. avdd5 45 gc0 external gain control output lsb - avdd5 46 gc1 external gain control output msb - avdd5 47 rxn0 analog receive negative input gain 0 echo filter output avdd5 48 rxp0 analog receive positive input gain 0 echo filter output avdd5 49 rxn1 analog receive negative input gain 1 (most sensitive input) echo filter output avdd5 50 rxp1 analog receive positive input gain 1 (most sensitive input) echo filter output avdd5 53 iref current reference tx dac/dace decoupling network avdd2 55 ivco current reference vco dac vco bias network avdd1 56 vcxo vxco control current vcxo filter avdd1 59 xtali xtal oscillator input pin crystal + varicap avdd1 60 xtalo xtal oscillator output pin crystal + varicap avdd1 digital interface 1 tx1 digital transmit input, parallel data - dvdd2 2 tx0 digital transmit input, parallel data - dvdd2 7 ctrlin serial data input (settings) async interface dvdd2 9 clkm master clock output, f = 35.328mhz load = cl<30pf dvdd2 10 clnib nibble clock output, f = 17.664mhz (osr = 2) or ground (osr = 4) load = cl<30pf dvdd2 11 clwd word clock output, f = 8.832/4.416mhz load = cl<30pf dvdd2 12 rx3 digital receive output, parallel data load = cl<30pf dvdd2 13 rx2 digital receive output, parallel data load = cl<30pf dvdd2 14 rx1 digital receive output, parallel data load = cl<30pf dvdd2 15 rx0 digital receive output, parallel data load = cl<30pf dvdd2 18 pdown power down select, "1" = power down power down input dvdd2 20 resetn reset pin (active low) rc- reset dvdd2 22 gp0 general purpose output 0 (on avdd 1) echo filter output avdd 33 gp1 general purpose output 1 (on avdd 1) echo filter output avdd 43 gp2 general purpose output 2 (on avdd 1) echo filter output avdd 63 tx3 digital transmit input, parallel data load = cl<30pf dvdd2 64 tx2 digital transmit input, parallel data load = cl<30pf dvdd2 19, 21 res reserved must be connected to dvss (input) - 36, 37, 39, 40, 57 res reserved must be connected to avss (input) -
ST70134A 6/22 supply voltages 8 dvss1 - dvss - 16 dvdd1 digital i/o supply voltage dvdd - 17 dvdd2 digital internal supply voltage dvdd - 23 avss3 - avss - 27 avdd3 adc supply voltage avdd - 28 avdd4 tx pre - drivers supply avdd - 34 avss4 - avss - 35 avss5 - avss - 41 avdd5 ct filter supply avdd - 42 avdd6 lna supply avdd - 51 avss6 - avss - 52 avss2 - avss - 54 avdd2 dac and support circuit avdd - 58 avdd1 xtal oscillator supply voltage avdd - 61 avss1 - avss - 62 dvss2 - dvss - spares 3 nu3 not used inputs dvss - 4 nu2 not used inputs dvss - 5 nu1 not used inputs dvss - 6 nu0 not used inputs dvss - 29 nc0 - - - 30 nc1 - - - figure 3 : grounding and decoupling networks numbers name function pcb connection supply 10 m f 100nf 10 m f 100nf vrap pin vran pin 10 m f 10 m f 100nf 10 m f vref pin iref pin 100nf analog vdd 4.7 m h l1 10 m f 100nf 100nf avdd (each pin 100nf 10 m f 10 m f agnd pin vcoc pin must have its own capacitor)
ST70134A 7/22 block diagram application principle is described in figure 4. a lp filter may be used on the tx path to reduce dmt sidelobes and out of band noise influence on the receiver. on the rx path, a hp filter must be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver. the pots filter is used in both directions to reduce crosstalk between adsl signals and pots speech and signalling. low pass pots fil- ter can be very simple for lite - adsl application (see figure 4). rx path speech filter an external bi-directional lc filter for up and downstream pots service splits the speech sig- nal from the adsl signal to the pots circuits. the adsl analog front end integrated circuit does not contain any circuitry for the pots service but it guarantees that bandwidth is not disturbed by spurious signals from the adsl-spectrum. channel filters the external analog circuits provide partial echo cancellation by an analog filtering of the transmit upstream signal. this is feasible because the upstream and the downstream data are modu- lated on separate carriers (fdm) (see figure 4). signal to noise performance rx- path sensitivity at maximum gain the rx path sensitivity at the maximal rx-agc of the receiver is defined at -140dbm/hz (for 100 w ref) on the line. this figure corresponds to the equivalent input noise of 31nvhz -1/2 seen on the line. the maximum noise density within the pass band can exceed the average value as follows: rx path (max agc setting): <100nvhz -1/2 @ 138khz <31nvhz -1/2 for 250khz < f * for adsl over isdn, instead of sc2, hc2 1.1mhz lp filter is programmed. figure 4 : block diagram vcodac xtal driver 56 vcxout 60 59 35.328mhz 48 50 47 49 rxn(0:1) rxp(0:1) lp 1.1mhz hc1 13 bits a/d converter 7 20 12 10 9 11 lna pd 31 32 lp 138khz sc2 * 12 bits d/a converter -15.0db txp txn lpf grx 50k w r 2r 2r r gtx line driver 1 2 txn hp potsfilter lp potsfilter pots 1.1 line zo = 100 w 4 master clock 35.328mhz nibbles 17.664mhz word 8.832/4.416mhz rxn ctrlin resetn to st70135 50k w 13 14 15 hpf + attenuator
ST70134A 8/22 rx-path noise at minimum gain at the minimum agc the total average thermal noise of the analog rx-path at the adc input should be lower than the adc quantisation noise. the maximum noise density within the pass band can exceed the average value as follows: rx path (min agc setting) <500nvhz -1/2 @ 138khz < f these noise specifications correspond to 10bit resolution of the complete rx-path. agc of rx path the agc gain in the rx-path is controlled through a 5-bits digital code. four inputs are provided for rx input and the selection is made with the rxmux bits of the ctrlin interface. this can be used to make lower gain paths in case of high input signal. rx filters the combination of the external filter (an lc lad- der filter typically) with the integrated lowpass fil- ter must provide: C echo reduction to improve dynamic range. C dmt sidelobe and out of band (anti-aliasing) at- tenuation. C anti alias filter (60db rejection @ image frequency). rx filters the integrated filter have the following character- istics: table 3 : rx common-mode voltage description value/unit common mode signal vcm at rxin1 and rxin2: 1.6v < vcm <1.7v table 4 : agc characteristics description value/unit input referred noise(max. gain) 31nvhz -1/2 max. input level 1vpd max. output level 1vpd gain range 0 to 31db with step = 1db gain and step accuracy 0.3db table 5 : integrated hc filter characteristics description value / unit maximum input level 1vpd maximum output level 1vpd type 3rd order butterworth frequency band 1.104mhz (0% setting, see below) frequency tuning -43.75% -> +0% max. in-band ripple 1db matlab model default cut off frequency @ -3db actual cut off @ -3db hc freq. selection register [b, a] = butter (3, w0, 's') f0 = 1560khz w0 = 2 * pi * f0/((20 + n)/16) n = -4,..,3 see (afe settings,table 19) table 6 : phase characteristic description value / unit total rx filter group delay < 50 m s @ 138khz < f < 1.104mhz total rx filter group delay distortion < 15 m s @ 138khz < f < 1.104mhz
ST70134A 9/22 figure 5 : hc filter mask for rx note: the total rx path (including adc) group delay distortion is 16 m s (i.e. = 15 m s + 1 m s of adc) linearity of rx linearity of the rx analog path is defined by the im3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.5vpd amplitude (total 1vpd) at the output of the rx - agc amplifier (i.e: before the adc) for the case of minimal agc setting. table 7 lists the rx path intermodulation distortion (as s/im3 ratio) in downstream and upstream band- width. power supply rejection the noise on the power supplies for the rx path must be lower than the following: <50mvrms in band white noise for any avdd. in this case, psr (power supply rejection) of st70134 rx path is lower than -43db. table 7 : linearity of rx f1 (0.5vpd) f2 (0.5vpd) 300khz 200khz 500khz 400khz 700khz 600khz s/im3 (agc = 0db) 59.5db @ 100khz 53.5db @ 400khz 43.5db @ 700khz 42.5db @ 800khz 59.5db @ 300khz 48.0db @ 600khz 48.0db @ 500khz 42.5db @ 800khz table 8 : rx filter to a/d interface rx filter to a/d maximal level: 1vpd = full scale of a/d table 9 : a/d converters numbers of bits: 12bits minimum resolution of the a/d converter 11bits linearity error of the a/d converter <1lsb (out of 12bits) full scale input range: 1 vpdif 5% sampling rate: 8.832mhz (or 4.416mhz in osr = 2 mode) maximum attenuation at 1.1mhz: <0.5db without in-band ripple maximum group delay: <3 m s maximum group delay distortion: <1 m s 5db 36db 50db 1db 0db 30 1104 2208 7728 16 560 khz amplitude
ST70134A 10/22 tx pre-driver capability the pre-driver drives an external line power amplifier which transmits the required power to the line. tx filter the tx filter acts not only to suppress the dmt sidebands but also as smoothing filter on the d/a conver- tor's output to suppress the image spectrum. for this reason it must be realized in a continuous time approach. atu-r tx filter the purpose of this filter is to remove out-of-band noise of the tx path echoed to the rx path. in order to meet the transmitter spectral response, an additional filtering must be (digitally) performed. the inte- grated filter has the following characteristics: note: the total tx path (including dac) group delay distortion is 16 m s (i.e. = 15 m s + 1 m s of dac). table 10 : tx pre-driver tx drive level to the external line driver for max. agc setting 1.5 vpdif external line driver input impedance: resistive capacitive > 500 w < 30pf pre-driver characteristics: closed loop gain: -15db...0db with step = 1db output characteristics output offset voltage (0db) < 10mv output noise voltage (0db) < 150nvhz -1/2 @ f > 250khz < 500nvhz -1/2 @ 34.5khz < f < 138khz 0db output common mode voltage: 1.6v < vcm < 1.7v table 11 : integrated sc filter characteristics description value/unit maximum input level 1vpd maximum output level 1vpd type 4th order chebytchef frequency band 138khz (0% setting see below) frequency tuning -25% -> +25% max. in-band ripple 1db matlab model default cut-off frequency @ -3db actual cut-off @ -3db sc frequency selection register [b,a] = cheby1 (4,0.5,w0,'s') {ripple = 0.5} f0 = 151.8khz w0 = 2*pi*f0/((17+n)/16) n = -4,..,3 see (afe settings, table 19) total tx filter group delay < 50 m s @ 34.5khz < f < 138khz total tx filter group delay distortion < 20 m s @ 34.5khz < f < 138khz
ST70134A 11/22 figure 6 : sc filter mask for tx linearity in tx linearity of the tx is defined by the im3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.5vpd amplitude (total 1vpd) at the output of the pre-driver for the case of a total agc = 0db. tx idle channel noise the idle channel noise specifications correspond with 11bit resolution of the complete tx-path. tx idle channel output noise on txp, txn. power supply rejection the noise on the power supplies for the tx-path must be lower than the following: < 50mvrms in-band white noise for avdd. < 15mvrms in-band white noise for pre-driver avdd. vcxo a voltage controlled crystal oscillator driver is integrated in st70134. the nominal frequency is 35.328mhz. the quartz crystal is connected between the pins xtali and xtalo. the principle of the vcxo control is shown in figure 7. table 12 : d/a converter (a current steering architecture is used) description value / unit numbers of bits: 12bits minimum resolution of the d/a converters 11bits linearity error of the a/d converter <1lsb (out of 12bits) full scale input range: 1 vpdif 5% sampling rate: 8.832mhz (or 4.416mhz in compatible mode) maximum group delay: <3 m s maximum group delay distortion: <1 m s table 13 : linearity in tx f1 (0.5vpd) 80khz f2 (0.5vpd) 70khz s/im3 (agc = 0 db) 59.5db (@ 60khz, 90khz) table 14 : tx idle channel noise for max agc setting (0db) in-band noise out-of-band noise 1.6 m vhz -1/2 150nvhz -1/2 @ 34.5khz -138khz @ 250khz -1.104mhz for min agc setting (=-15db) in-band noise 500nvhz -1/2 @ 34khz -138khz amplitude 0db 1db 20db 30 138 250 khz
ST70134A 12/22 the information coming from the digital processor via the ctrlin path is used to drive an 8-bit dac which generates a control current. this current is externally converted and filtered to generate the required control voltage (range:-15v to 0.5v) for the varicap. the vcxo circuit characteristics are given in table 15. n.b: frequency tuning range is proportional to the crystal dynamic capacitance cm. figure 7 : principle of vcxo control the tuning must be monotonic with 8-bit resolution with the worst-case tuning step of <2ppm/lsb (8-bit). the time constant of the tuning must be variable from 5s to 10s through an external capacitor cs (r = 1m w 30%). this determines the speed of the vcxo in normal operation (slow speed in "show time") with filtered vcxo. for faster tracking, the previous filter is not used and the speed depends on ctrt. digital interface control interface the digital setting codes for the st70134 configuration are sent over a serial line (ctrlin) using the word clock (clwd). the data burst is composed of 16 bits from which the first bit is used as start bit ('0'), the three lsbs being used to identify the data contained in the 12 remaining bits. table 15 : vcxo circuit characteristics symbol parameter minimum nominal maximum note f abs absolute frequency accuracy -15ppm 35.328mhz +15ppm f range frequency tuning range 50ppm io vcxo output current 100 m a rref = 16.5k w avdd = 3.3v ii reference input current 100 m a 1ma avdd = 3.3v dac 8 bits 1m w 30% filtered vcxo (see ctrlin table) 44 vcoc cs avdd 7 ctrlin 55 ivco avdd rref avdd/22 avdd/2 li 56 vcxo clk35 60 59 cp xtali xtalo ct rt agnd io = li -15v
ST70134A 13/22 note 1. after initialization, this bit has to be cleared (0) to make the device properly operate. table 16 : control interface bit mapping msb lsb rx settings b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0x 0 0 0 external gain control gc1 (init = 0) 0 x 0 0 0 external gain control gc0 (init = 0) 0 0 0 0 0 rx input selected = rxin0, rxip0 (init) 0 1 0 0 0 rx input selected = rxin1, rxip1 0 0 0 0 0 0 0 0 0 agc rx gain setting 0db (init) 0 00001 00 0agc rx gain setting 1db 0 xxxxx 0 0 0agc rx gain setting xdb 0 1 1 1 1 1 0 0 0 agc rx gain setting 31db 0 0 0 0 0 0 normal mode filter selection (init) 0 0 1 0 0 0 force hc2 for rx path, tx grounded 0 1 0 0 0 0 force hc1 for rx path 0 1 1 0 0 0 normal mode filter selection b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tx settings 0 0 0 0 0 0 0 1 transmit tx - agc setting -15db (init) 0 0 0 0 1 0 0 1 transmit tx - agc setting -14db 0 x x x x 0 0 1 transmit tx - agc setting (x - 15) db 0 1 1 1 1 0 0 1 transmit tx - agc setting 0db 0 0 0 0 0 0 0 1 not used (init) 0 x x x 0 0 1 general purpose output (gpo) setting (init = 000) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 afe settings 00 0 1 0 normal mode (digital path) (init) 01 0 1 0 digital loopback (digital tx to digital rx - dac not used) 0 0 0 1 0 normal mode (analog path) 01 010 analog loopback (rxi to txi - adc not used) 1 (init) 0 0 0 1 0 vco dac disabled 0 1 0 1 0 vco dac enabled (init) 0 0 0 1 0 hc2 filter disabled (init) 0 1 0 1 0 hc2 filter enabled
ST70134A 14/22 * for each filter, 8 possible frequency values (see table 5 and table 11). notation is 2's complement range from -4 = 100b +3 = 0 11b. fc is the frequency band (-1db) table 17 : control interface bit mapping (continued) msb lsb afe settings b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 1 0 osr set to 4 (init) 0 1 0 1 0 osr set to 2 0 1 1 1 0 1 0 sc freq. selection: fc = 138khz (init) * 0 0 1 1 0 1 0 sc freq. selection: fc ~ 110khz * 0 1 0 1 0 1 0 sc freq. selection: fc ~ 170khz * 0 1 0 0 0 1 0 hc freq. selection: fc = 1.104mhz (init) * 0 0 1 1 0 1 0 hc freq. selection: fc ~ 768khz * 0 0 0 1 0 vcxo output not filtered ("show-time") (init) 0 1 0 1 0 vcxo output filtered b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 vco dac value settings 0 0 0 0 0 0 0 0 0 0 1 1 vco dac current value @ minimum 0 xxxxxxxx 0 1 1vco dac current value @ x 0 11111111 01 1vco dac current value @ maximum b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 power down analog block settings 0 00000000000010 0init 00 1 0 0 txd active 01 10 0txd in powerdown 00 100n.u. 01 100n.u. 00 100adc active 01 100adc in powerdown 001 100hfc2 active 0 1 1 1 0 0 hfc2 in powerdown 001 100hfc1 active 0 1 1 1 0 0 hfc1 in powerdown 0 0 1 1 0 0 scf2 active 011100scf2 in powerdown 0 0 1 0 0 lna active 0 1 1 0 0 lna in powerdown 001100dac active 0 1 1 1 0 0 dac in powerdown 0 0 1 0 0 vcodac active 0 1 1 0 0 vcodac in powerdown 0 0 1 0 0 xtal active 0 1 1 0 0 xtal in powerdown b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 reserved 0 x x x x x x x x x x x x 1 0 1 reserved 0 x x x x x x x x x x x x 1 1 0 reserved 0 x x x x x x x x x x x x 1 1 1 reserved
ST70134A 15/22 control interface timing the word clock (clwd) is used to sample at negative going edge the control information. the start bit b15 is transmitted first followed by bits b[14:0] and at least 16 stop bits need to be provided to validate the data. data set-up and hold time versus falling edge clwd must be greater than 10nsec. receive / transmit interface receive / transmit protocol the digital interface is based on 4 x 8.832mhz (35.328mhz) data lines in the following manner: if osr = 2 (osr bit set to 1) is selected, clknib is used as nibble clock (17.664mhz, disabled in normal mode), and all the rxi, txi, clkwd periods are twice as long as in normal mode. this ensures a compatibility with lower speed products. tx signal dynamic the dynamic of data signal for both tx dacs is 12 bits extracted from the available signed 16 bit repre- sentation coming from the digital processor. the maximal positive number is 2 14 -1, the most negative number is -2 14 , the 3 lsbs are filled with '0'. any signal exceeding these limits is clamped to the maximum value. the two sign bits must be identical. figure 8 : control interface table 18 : tx data bit map bit map/nibble n0 n1 n2 n3 txd0 not used data bit 1 data bit 5 data bit 9 txd1 not used data bit 2 data bit 6 data bit 10 txd2 not used data bit 3 data bit 7 data sign txd3 d0 = data bit 0 (lsb) data bit 4 data bit 8 data sign table 19 : tx nibble bit map n3 n2 n1 n0 sign sign d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 n.u. n.u. n.u. data clwd ctrlin start bit id. >=16 stop bits = high
ST70134A 16/22 rx signal dynamic the dynamic of the signal from the adc is limited to 13bits. those bits are converted to a signed (2's complement) representation with a maximal positive number of 2 14 -1 and a most negative number -2 14 . the 2 lsbs are filled with '0'. the two sign bits must be identical. table 20 : rx data bit map bit map/nibble n0 n1 n2 n3 rxd0 0 data bit 2 data bit 6 data bit 10 rxd1 0 data bit 3 data bit 7 data bit 11 rxd2 d0 = data bit 0 (lsb) data bit 4 data bit 8 data sign rxd3 data bit 1 data bit 5 data bit 9 data sign table 21 : rx nibble bit map n3 n2 n1 n0 sign sign d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 figure 9 : tx/ rx digital interface timing clkm 35.328mhz clwd 8.832mhz txdx/rxdx n0 n1 n2 n3 osr = 4 clknib 17.664mhz clwd 4.4162mhz txdx/rxdx n0 n1 n2 n3 osr = 2
ST70134A 17/22 receive / transmit interface timing the interface is a quadruple (rx, tx) nibble - serial interface running at 8.8mhz sampling (nor- mal mode). the data are represented in 16bits format, and transferred in groups of 4 bits (nib- bles). the lsbs are transferred first. the st70134 generates a nibble clock (clkm master clock in normal mode, clknib in osr = 2 mode) and word signals shared by the three interfaces. data is transmitted on the rising edge of the mas- ter clock (clkm/clknib) and sampled on the falling edge of clkm/clknib. this holds for the data stream from st70134 and from the digital processor. data, clwd setup and hold times are 5ns with reference to the falling edge of clkm/clknib. (not floating). data is transmitted on the rising edge of the mas- ter clock (clkm/clknib) and sampled on the low going edge of clkm/clknib. this holds for the data stream from st70134 and from the digital processor.data, clwd setup and hold times are 5ns with reference to the falling edge of clkm/ clknib. (not floating). power down when pin pdown = "1", the chip is set in power down mode. as the pdown signal is synchro- nously sampled, minimum duration is 2 periods of the 35mhz clock. in this mode all analog func- tional blocks are deactivated except: preamplifiers (tx), clock circuits for output clock clkm. pdown will not affect the digital part of the chip. anyway, after a pdown transition, the digital part status, is updated after 3 clock periods (worst case). the chip is activated when pdown = "0". in power down mode the following conditions hold: C output voltages at txp/txn = agnd C preamplifier is on with maximum gain setting (0db), (digital gain setting coefficients are over- ruled) C the xtal output clock on pin clkm keeps running. C all digital setting are retained. C digital output on pins rxdx don't care(not floating). in power-down mode the power consumption is 100mw. following external conditions are added: C clock pin clw is running. C ctrlin signals can still be allowed. C agnd remains at avdd/2 (circuit is powered up) C input signal at txdx inputs are not strobed. the pdown signal controls asynchronously the power-down of each analog module: C after a few m s the analog channel is functional C after about 100ms the analog channel delivers full performance reset function the reset function is implied when the resetn pin is at a low voltage input level. in this condition, the reset function can be easily used for power up reset conditions. detailed description during reset: (reset is asynchronous, tenths of ns are enough to put the ic in reset). all clock outputs are deactivated and put to logical "1" (except for the xtal and master clock clkm). after reset: (4 clock periods after reset transition, as worst case). C osr = 4 C all analog gains (rx, tx) are set to minimum value C nominal filter frequency bands (138khz, 1.104mhz) C lna input = "11" (max. attenuation) C vco dac disabled digital outputs are placed in don't care condition (non-floating). n.b. if a xtal oscillator is used, the reset must be released at last 10 m s after power-on, to ensure a correct duty cycle for the clk35 clock signal.
ST70134A 18/22 electrical ratings and characteristics absolute maximum ratings thermal data operating conditions (unless specified, the characteristic limits of 'static characteristics' in this document apply over an t op = -40 to 80c; v dd within the range 3 to 3.6v ref. to substrate. static characteristics digital inputs schmitt-trigger inputs: txi, ctrlin, pdown, resetn symbol parameter minimum maximum unit v dd any vdd supply voltage, related to substrate - 0.5 5 v v in voltage at any input pin -0.5 vdd +0.5 v t stg storage temperature -40 125 c t l lead temperature (10 second soldering) 300 c i lu latch - up current @80c 100 ma i av dd analog supply current @ 3.6v - normal operation 165 ma i av dd analog supply current @ 3.6v - power down 30 ma i dvdd analog supply current @ 3.6v - normal operation 56 ma i dvdd analog supply current @ 3.6v - power down 50 ma symbol parameter value unit r th j-amb thermal and junction ambient 50 c/w symbol parameter minimum maximum unit avdd avdd supply voltage, related to substrate 3.0 3.6 v dvdd dvdd supply voltage, related to substrate 2.7 3.6 v v in /v out voltage at any input and output pin 0 vdd v p d power dissipation 0.4 0.6 w t amb ambient temperature -40 80 c t j junction temperature -40 110 c symbol parameter test condition minimum typical maximum unit v il low level input voltage 0.3 x dvdd v v ih high level input voltage 0.7 x dvdd v v h hysteresis 1.0 1.3 v c imp input capacitance 3 pf
ST70134A 19/22 digital outputs hard driven outputs: rxi clock driver output: clkm, clnib, clkwd symbol parameter test condition minimum typical maximum unit v ol low level output voltage i out = -4ma 0.15 x dvdd v v oh high level output voltage i out = 4ma 0.85 x dvdd v c load load capacitance 30 pf symbol parameter test condition minimum typical maximum unit v ol low level output voltage i out = -4ma 0.15 x dvdd v v oh high level output voltage i out = 4ma 0.85 x dvdd v c load load capacitance 30 pf dc duty cycle 45 55 %
ST70134A 20/22 package mechanical data figure 10 : package outline tqfp64 dimension millimeter inch minimum typical maximum minimum typical maximum a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.18 0.23 0.28 0.007 0.009 0.011 c 0.12 0.16 0.20 0.0047 0.0063 0.0079 d 12.00 0.472 d1 10.00 0.394 d3 7.50 0.295 e 0.50 0.0197 e 12.00 0.472 e1 10.00 0.394 e3 7.50 0.295 l 0.40 0.60 0.75 0.0157 0.0236 0.0295 l1 1.00 0.0393 k 0 (minimum), 7 (maximum) 64 49 17 32 1 16 48 33 e c a1 a2 a d3 d1 d e3 e1 e l k l1 0,25 mm .010 inch gage plane 0,10 mm .004 inch seating plane b
ST70134A 21/22
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states http://www.st.com 22/22 ST70134A.pdf

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